This invention relates to integrated circuits, such as electrically-programmable, read-only-memory (EPROM) arrays, and to a circuit and method for ensuring the quality of fuse-link alterations by laser or other means.
In particular, the invention relates to avoiding or eliminating errors resulting from fuse-links that are not completely opened or closed during alteration.
An EPROM array is but one example of an integrated circuit that in which the circuit and method of this invention may be used. EPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen wordline select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen wordline select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EPROM array may contain thousands of cells. The sources of each cell in a column are connected to a source-column line. The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline.
During cell programming, appropriate programming voltages applied to the selected control-gate wordline and drain bitline to create a high-current condition in the selected channel region, injecting channel-hot electrons and/or avalanche-breakdown electrons across the channel oxide to the floating gate.
To improve manufacturing yield, redundant columns and rows of memory cells are used to replace columns or rows with defective memory cells. The integrated memory circuit may include a set of links or fuses that are programmed to provide address information pertaining to the columns or rows with the defective memory cells. Address information in the set of links or fuses is compared with the incoming addresses, and input and output data are routed to the redundant rows or columns.
Chips manufactured with "closed" electrical links as elements to program redundant address data may be programmed by electrically opening selected links with high currents and/or electric fields or may be programmed by using a laser to "explode" the link. Chips that are manufactured with "opened" electrical links between two layers may be programmed by causing the links to form resistive shorts.
For the first case, in which selected "closed" links are "opened" during programming, complete "opens" are not always formed. Marginally opened links can cause incorrect results at different operating conditions or sequences. Typically, these are screened or tested by some complex or some non-standard method. Often, a new screen test will have to be developed for each new device.
There is a need for a circuit and method to test the resistance of the open state and guarantee a high level of safety margin to ensure that the open state will not be misread. A prior-art, basic method for reading redundant data from fuses is the use of a P-channel transistor with source-drain path connected between supply voltage source Vcc and an intermediate node. Individual polysilicon links are connected in series with the source-drain paths of gate devices or transistors. Each series-connected link and gate transistor is connected between the intermediate node and reference potential Vss. The gate of each gate device is connected to an address buffer output. The gate of the P-channel transistor is normally connected to a source of reference potential, which may be ground or Vss. The polysilicon links are low enough in resistance that when only one gate device is conductive, the voltage at the intermediate node will be low enough that, when applied to an inverter, will cause the output of that inverter to be a high voltage. For example, if two of the polysilicon links are opened to program an address, the input to the inverter will be at a low voltage as long as the gate devices in series with the remaining links are conductive. However, when that address is applied at terminals of the gate devices, a "match" occurs, the transistors in series with the remaining links are not conductive, and the voltage at the intermediate node goes to a higher voltage. However, if one of polysilicon links is not opened completely, the voltage at the intermediate node may not go as high as the supply voltage Vcc and may cause the voltage at the output of the inverter to be unstable or may cause an invalid output state.